1. Field of the Invention
The present invention relates to user-programmable circuits. More particularly, the present invention relates to field programmable gate array (FPGA) integrated circuits and to arrangements for flip-flop and logic circuits in FPGA architectures.
2. The Prior Art
Modern FPGA functionality is provided by logic modules and flip-flops. Logic modules can be n-input look-up-tables (n-LUTs) or any other kind of function generators with n inputs, where (n>1). The flip-flops can be simple D type flip-flops, or they can have additional functionality such as CLEAR, RESET, LOAD, and ENABLE. These additional functions (with the exception of ENABLE) can be synchronous with the clock (CLK) or asynchronous (or both.)
Logic modules and flip-flops are often grouped into clusters that may typically vary in size from four to more than twenty. The clustering provides no additional functionality; it is done for routing convenience. In addition to the functionality provided by the logic modules and flip-flops, the FPGAs may include other types of functional blocks such as multipliers, RAMs, FIFOs, etc.
The most common arrangement of logic modules and flip-flops is shown in FIG. 1. In this kind of arrangement, the Y output of a logic module 10 directly drives the D input of the flip-flop 12. The A, B, C, and D data inputs of the logic module 12 are each driven by a multiplexer; multiplexer 14 drives data input A, multiplexer 16 drives data input B, multiplexer 18 drives data input C, multiplexer 20 drives data input D. Each of multiplexers 14, 16, 18, and 20 have a plurality of data inputs that are driven from routing tracks as is known in the art. Multiplexer 22 allows the Q output of flip-flop 12 to be used as an additional input to the D data input of logic module 10. The CLK input of flip-flop 12 is driven by the output of multiplexer 24, which allows selection between the various clock resources at its data inputs.
The arrangement shown in FIG. 1 has been used in earlier anti-fuse based FPGA products designed and marketed by Actel Corporation of Mountain View Calif. This is an economical in arrangement in terms of routing fabric usage, but it is also the most limited in terms of flexibly packing logic functions and flip-flops together. Unless the flip-flop is packed with the logic that drives it, the logic block functionality must be used as a feed through buffer and is thus wasted. In typical FPGA designs, this limitation causes a large number of isolated flip-flops to be present that are not packed together with logic modules.
The packing limitations of the arrangement shown in FIG. 1 can be improved significantly by allowing configurable connections between logic modules and the flip-flops, as shown in FIG. 2. An additional multiplexer 26 permits selection of the source of the D input to the flip-flop 12 between the Y output of the logic module 10 and the output of multiplexer 20 that drives the D input to the logic module 10.
The arrangement shown in FIG. 2 is very commonly used in various products by FPGA vendors. As will be appreciated by persons of ordinary skill in the art, the logic module 10 in the arrangement of FIG. 2 is no longer wasted if the D-input of the flip-flop 12 is not driven from within that module. On average, this improves the packing efficiency by packing 20% more flip-flops with logic modules. However, even this arrangement has limitations when the logic module 10 does not drive the flip-flop 12. The total number of combined data inputs to the logic module 10 and to the flip-flop 12 must be “n”, the same as the maximum number of inputs to the logic module. This either means that the logic module is used in a limited role by computing a logic function of (n−1) inputs, or that one of the inputs of the logic module must be driven from the Q-output of the flip-flop.
Even though the arrangement shown in FIG. 2 improves the packing density, the improvement comes with a small performance penalty due to the delay through the flip-flop multiplexer 26 between the logic module 10 and the flip-flop 12. This is typically a small delay that is well worth the increase in packing density, as long as the multiplexer 26 remains a single-level multiplexer.